A Methodology Based on Reduced Complexity Algorithm for System Applications Using Microprocessors

Many communication, control, and information processing subsystems (such as data equalizer, array processor, whitening filter, dynamical system identifier, etc.) are modeled by linear systems incorporating tapped delay lines (TDL). Such optimized subsystems result in full precision multiplications in the TDL. In order to reduce complexity and cost in a microprocessor implementation, these multiplications (consisting of multiple-shift-and-add instructions) can be replaced by single-shift instructions which are equivalent to powers of two multiplications. Since in general the obvious operation of rounding the infinite precision TDL coefficients to the nearest powers of two usually yield quite poor system performance, we consider the optimum powers of two coefficient solution. Detailed explanations on the use of branch-and-bound algorithm for finding the optimum powers of two solutions are given. Specific demonstration of this methodology to the design of a linear data equalizer and its implementation in assembly language on a 8080 microprocessor with a 12 bit A/D converter are reported. This simple microprocessor implementation with optimized TDL coefficients achieves a system performance comparable to the optimum linear equalization with full precision multiplications for an input data rate of 300 baud. The philosophy demonstrated in this implementation is fully applicable to many other microprocessor controlled information processing systems. T.Y. Yan is with the Communication Research Section of Jet Propulsion Laboratory, Pasadena, California 91109, and K. Yao is with the Electrical Engineering Department, University of California, Los Angeles, California 90024.